In recent years, 3D stacking technology has been developing to shorten the length of the leads between the chips, to reduce the dimension of the devices, and to establish a 3D stacked structure of the chips in the semiconductor industry, wherein through-substrate vias are important components in 3D stacking technology for connecting chips stacked vertically.
In the application of the through-substrate vias, in addition to through-silicon vias (TSVs), through-glass vias (TGVs) are also currently available. However, due to coefficient of thermal expansion (CTE) mismatch between the filling material in the through-glass vias and glass and the glass substrate being more brittle and less elastic, uneven thermal stress is generated around the through-glass vias, causing peeling and pop-up in the through-glass vias, and even causing chip cracks.
In the known method for reducing stress, changing the material and the appearance of the through-glass vias, or adding other materials to the structure are usually adopted.